Semiconductor devices are packaged in a variety of package types such as in a dual-in-line package ("DIP"), thin shrunk small outline package ("TSSOP"), ceramic DIP package ("CERDIP"), plastic DIP ("PDIP"), zig-zag-in-line package ("ZIP"), small outline integrated circuit ("SOIC"), small outline J-bend lead package ("SOJ"), small outline package ("SOP"), and a thin small outline package ("TSOP").
Typically, integrated circuit packages contain a single integrated circuit die mounted on a centralized die pad within the package. Other integrated circuit packages, typically referred to as multi-chip modules ("MCM"), contain two or more integrated circuit dice mounted on a centralized die pad or respective centralized die pads within the package. The integrated circuit dice in an MCM are often LSI, VLSI, and/or ULSI circuits.
Often a need exists to add circuit devices to existing devices and device designs. A packaged single integrated circuit die or an MCM may require multiple additional circuit devices. For semiconductor devices, there is frequently the need, for example, to add multiple function circuits to protect and enhance device performance. Examples of such protection and performance enhancing circuits are temperature sensing circuits with voltage and current detection and electrostatic discharge ("ESD") protection circuits.
At present, the conventional methods typically achieve an additional function by adding a circuit(s) externally to the semiconductor package ("external approach") or integrating the additional circuit(s) with the semiconductor device on the same wafer ("monolithic approach") within a package.
The external approach suffers from several disadvantages. For example, the external approach incurs additional packaging costs and additional assembly time in relation to the monolithic approach. The external approach also typically requires more space than a comparable monolithic approach.
The monolithic approach exhibits several disadvantages as well. The monolithic approach often requires integrating a simple process(es) associated with the additional circuit(s) with a relatively complex process during fabrication. The simple process requires compatibility with all previous and subsequent process steps. Additionally, the monolithic approach typically provides a common base to all circuits which can produce inter-circuit interference. Furthermore, integrating an additional circuit(s) to a previously defined integrated circuit design, especially after production has begun, incurs substantial associated expenses such as new layout costs, mask preparation, and process compatibility analysis.